Verilog Reference Guide Conditional Assignment (last edit: 26. January 2023)
Definition
Syntax 
  alias AliasName [: Datatype] is Name [Signature];

  Signature = [TypeName, ...] return TypeName
Placement 
  PACKAGE Pack IS
    ... 
  END PACKAGE Pack;
 
  PACKAGE BODY Pack IS
    ... 
  END PACKAGE BODY Pack;
 
  Blk:BLOCK 
    ... 
  BEGIN 
    ... 
  END BLOCK Blk;
 
  ENTITY Ent IS
    ... 
  BEGIN 
    ... 
  END ENTITY Ent;
 
  ARCHITECTURE Arc OF Ent IS
    ... 
  BEGIN 
    ... 
  END ARCHITECTURE Arc;
 
  CONFIGURATION Conf OF Ent IS
    ... 
  END CONFIGURATION Conf;
 
  Proc:PROCESS(...) 
    ... 
  BEGIN 
    ... 
  END PROCESS Proc;
 
  PROCEDURE P(...) IS
    ... 
  BEGIN 
    ... 
  END PROCEDURE P;
 
  FUNCTION F(...) RETURN Tp IS
    ... 
  BEGIN
    ... 
  END FUNCTION F;
Rules
Each signal used in alias statement needs to be same net type. A wire, inout etc.
Each signal used in alias must be of same width.
Things to remember
Synthesis
Example 
  module mux2( input logic [3:0] mux_i0, mux_i1,
               input logic mux_c,
               output logic [3:0] mux_o);

    assign mux_o = mux_c = ? mux_i1 : mux_i0

ÿen??ule
if mux_c is 1, then mux_o = mux_i1,
if mux_c is 0, then mux_o = mux_i0
See Also